1986 Year’s Transparent Silicon Membranes Used for Ion Implantation Self Annealing

Tu Xiang Zheng

 

The above picture shows a thin silicon membrane supported by a thick silicon frame. In order to indicate the very small thickness of the thin silicon membrane a business card is placed under the silicon membrane. A letter “POSIFA” of the business card can be seen clearly through the thin silicon membrane, which means that the membrane is very thin so as to be transparent. Actually the thin silicon membrane is n-type single crystal silicon with a 3 Ω-cm resistivity and has 1 micron in thickness and 1cm in diameter. In general when the thickness of a silicon membrane is less than 5 micron the membrane can transparent part of the visible light.

The thin silicon membrane was fabricated by the present author in early 1986 year. At that time the present author was asked to fabricate a thin single crystal silicon membrane for the studies of single crystal silicon ion implantation self annealing. Thermal annealing in a furnace is the technique normally used to remove lattice damage and restore the electrical properties of ion implanted single crystal silicon. As an alternative, the annealing can be done utilizing the heating effect produced by the same ion beam during the implantation process. The heating temperature should be very high so that the ion implanted silicon layer can enter epitaxial regrowth phase. On the other hand the cooling of the silicon layer is slow enough allowing epitaxial regrowth to be carried out. This is why the thin single crystal silicon membrane is required, which can provide an excellent thermal insulation.

Etching stop technology enables the formation of thin single crystal silicon membranes. An early etch stop technology is based on P⁺ etch stop layers. This is because the rate of silicon etching depends on the boron concentration and decreases so dramatically that anisotropic etchants, especially KOH, barely attack boron doped (P⁺) silicon layers with boron concentrations around 10^-19cm^-3. Unfortunately, heavy boron doped silicon membrane can not be used for the studies of single crystal silicon ion implantation self annealing. The base resistivity of the silicon to be implanted should be higher than 1 Ω-cm so as to be able to fabricate semiconductor devices.

A lightly doped p-n junction can be used as an etch stop by applying a bias between the wafer and the etchants. But the etchants are limited to be alkali such as KOH. It has long been known that metal impurities including alkali metals (Na, K, and Li) can affect a variety of silicon device characteristics, including junction leakage, surface and bulk recombination, emitter to collector shorting, and gate oxide integrity. In addition, in order to apply a positive voltage to the silicon wafer a metal contact needs to be made thereon, which is not accepted by the silicon device fabrication due to the same reason.

The present author did a lot of literature survey and did not find any useful reference materials. The present author knew that he faced to a tough target and a difficult challenge, but he did not give up. He tried many new ways and finally found the best one is selective formation and selective etching of porous silicon.

Porous silicon is a material which is formed by anodization that is electrochemical oxidation of single crystal silicon in concentrated hydrofluoric acid (HF) solutions. The formation reaction is highly dependent on the type and level of silicon doping, and the material can be selectively formed on particular regions of a wafer that present appropriate doping characteristics obtained by diffusion or ion implantation.

The process started with an n/n ⁺ epitaxial silicon wafers with heavily boron doped substrates. The silicon wafer is patterned on the frond side and inserted into an etching cell for electrical contacting. The silicon wafer serves as anode. Two types of etching cells are used: double-cells and single-cells. By the use of a double cell the wafer is contacted with the aid of electrolyte on both sides. That means the electrodes of HF-resistant material (platinum or silicon) are placed into electrolyte and the induced current /applied voltage goes through the electrolyte to contact the wafer. The positive potential is applied on the back side and the negative potential on the front side of the silicon wafer, where the porous layer is generated. Then the porous silicon is etched selectively so as to leave a thin silicon membrane suspending by a silicon frame of the wafer. The etchants such as a mixture of HF and H₂O₂  may be used for selective etching of porous silicon.